1. Field of the Invention
The invention pertains to the architecture of integrated circuits that perform a special type of signal digital processing operation. More precisely, the digital processing considered herein is a double weighted addition, in rows and then in columns, of digital values x(i,j) of a matrix of n x n digital values.
With coefficients x (i, j), where i is a row index of the matrix and j is a column index, it is sought to produce a matrix of coefficients C(u,v) where u is a row index and v is a column index with: ##EQU1##
Using input electrical signals representing the digital values x(i,j), nxn signals representing coefficients C.sup.i (v) are produced at first. Each coefficient C.sup.i (v) represents a weighted addition of the values x(i,j) of the row i assigned coefficients f(j,v); v represents a column index varying from 0 to n-1 and there are n coefficients C.sup.i (v) for each row with an index i. This operation is called row transformation.
Using the nxn signals representing the coefficients C.sup.i (v), nxn signals representing the coefficients C(u,v) are produced. Each coefficient C(u,v) is a weighted addition of the values C.sup.i (v) of the column v assigned coefficients g(i,u); u represents a row index varying from 0 to n-1 and n coefficients C(u,v) are produced for each column with an index v. This operation is the column transformation.
This type of digital processing is encountered especially when making so-called cosine transformations where the coefficients f(j,v) and g(i,u) have the form cos (2i+1) u.pi./2n: these transformations are useful for facilitating the compression of data in digital transmissions of signals, and especially for the digital transmission of images.
2. Description of the Prior Art
The architectures of integrated circuited circuits used to make this type of transformation are relatively complicated because they have to enable real-time processing, i.e. the transfer rate of the digital data to be processed is imposed at the input of the circuit and the transfer rate of the processed data at the output should be as fast as the transfer rate at the input. Of course, this transfer rate is high: for example, for the digital transmission of images, it is sought to be able to process a block of 16.times.16 digital values (256 pixels) in less than 20 microseconds since successive blocks of 256 values appear at the input of the circuit with a periodicity about 20 microseconds.
FIG. 1 is a block diagram of a fairly simple integrated circuit architecture which may be devised to perform, on one and the same integrated circuit chip, the complete transformation of a block of nxn digital values x(i,j) into a block of nxn coefficients C(u,v).
In this diagram, there is a first operator CTL that performs the row addition, a second operator CTC that performs the column addition, two memories, MEM 1 and MEM 2, to store values representing the coefficients C.sup.i (v) and two routing switches, AIG 1 and AIG 2, to set up connection paths between, firstly, the operator CTL and the memories MEM 1 and MEM 2 and, secondly, between these memories and the operator CTC. The assembly is controlled by a sequencer SEQ.
A block of nxn data x(i,j) to be processed is brought by an input bus E to the row transform operator CTL which produces nxn digital data representing nxn digital coefficients C.sup.i (v): This data is stored in the nxn addresses of the memory MEM 1 (memory of nxn words). The rate at which the blocks of nxn data are processed is, for example, one block per 20 microseconds. One datum x(i,j) appears, for example, every 70 nanoseconds (for nxn=256).
To process the following block of nxn values x(i,j), the circuit CTL receives the successive values x(i,j) and performs the row transformation. However, this time, the sequencer SEQ controls the routing switch AIG1 so as to store the results C.sup.i (v) in the second memory MEM2. During this time, the data previously recorded in the memory MEM1 is applied in the form of input digital values to be processed, through the routing switch AIG 2, to the column transformation circuit CTC which produces the coefficients C(u,v) at its output.
This process is continued: alternately, a block of nxn coefficients C.sup.i (v) is stored in one of the memories while a block of coefficients C.sup.i (v), recorded at the previous period in the other memory, is processed.
This architecture is elegant but requires two memories each capable of storing nxn data C.sup.i (v). For it must be clearly understood that, for it to be possible to perform a column transformation on the coefficients C.sup.i (v), all the coefficients C(v) of one and the same column v should be memorized. Now, since these coefficients C.sup.i (v) reach the circuit CTL row by row, and not line by line, this means in practice that the column transformation can start only when all the coefficients C.sup.i (v) of the matrix have reached the circuit CTL. This is why the architecture of FIG. 1 uses two memories that work alternately. Furthermore, it must be noted that if the data C.sup.i (v) is registered in a memory row by row (i being the row index), then the said data should be read in the following period column by column (v being the column index).